.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 11, 0	sdk_version 11, 3
	.globl	__Z10F32fromI32P6Vec128RKS_     ; -- Begin function _Z10F32fromI32P6Vec128RKS_
	.p2align	2
__Z10F32fromI32P6Vec128RKS_:            ; @_Z10F32fromI32P6Vec128RKS_
	.cfi_startproc
; %bb.0:
	; InlineAsm Start

	ld1.4s	{ v0 }, [x1]
	scvtf.4s	v1, v0	; float32 <- int32   
	st1.4s	{ v1 }, [x0]	; [x0] = v1          

	; InlineAsm End
	ret
	.cfi_endproc
                                        ; -- End function
	.globl	__Z10F64fromI64P6Vec128RKS_     ; -- Begin function _Z10F64fromI64P6Vec128RKS_
	.p2align	2
__Z10F64fromI64P6Vec128RKS_:            ; @_Z10F64fromI64P6Vec128RKS_
	.cfi_startproc
; %bb.0:
	; InlineAsm Start

	ld1.2d	{ v0 }, [x1]
	scvtf.2d	v1, v0	; float64 <- int64   
	st1.2d	{ v1 }, [x0]	; [x0] = v1          

	; InlineAsm End
	ret
	.cfi_endproc
                                        ; -- End function
	.globl	__Z10F32fromU32P6Vec128RKS_     ; -- Begin function _Z10F32fromU32P6Vec128RKS_
	.p2align	2
__Z10F32fromU32P6Vec128RKS_:            ; @_Z10F32fromU32P6Vec128RKS_
	.cfi_startproc
; %bb.0:
	; InlineAsm Start

	ld1.4s	{ v0 }, [x1]
	ucvtf.4s	v1, v0	; float32 <- int32   
	st1.4s	{ v1 }, [x0]	; [x0] = v1          

	; InlineAsm End
	ret
	.cfi_endproc
                                        ; -- End function
	.globl	__Z10F64fromU64P6Vec128RKS_     ; -- Begin function _Z10F64fromU64P6Vec128RKS_
	.p2align	2
__Z10F64fromU64P6Vec128RKS_:            ; @_Z10F64fromU64P6Vec128RKS_
	.cfi_startproc
; %bb.0:
	; InlineAsm Start

	ld1.2d	{ v0 }, [x1]
	ucvtf.2d	v1, v0	; float64 <- int64   
	st1.2d	{ v1 }, [x0]	; [x0] = v1          

	; InlineAsm End
	ret
	.cfi_endproc
                                        ; -- End function
	.globl	__Z10F32fromF64P6Vec128RKS_S2_  ; -- Begin function _Z10F32fromF64P6Vec128RKS_S2_
	.p2align	2
__Z10F32fromF64P6Vec128RKS_S2_:         ; @_Z10F32fromF64P6Vec128RKS_S2_
	.cfi_startproc
; %bb.0:
	; InlineAsm Start

	ld1.2d	{ v0 }, [x1]
	ld1.2d	{ v2 }, [x2]
	fcvtn	v1.2s, v0.2d	; lower-order F32    
	fcvtn2	v1.4s, v2.2d	; higher-order F32   
	st1.4s	{ v1 }, [x0]	; [x0] = v1          

	; InlineAsm End
	ret
	.cfi_endproc
                                        ; -- End function
	.globl	__Z10F64fromF64P6Vec128RKS_S2_  ; -- Begin function _Z10F64fromF64P6Vec128RKS_S2_
	.p2align	2
__Z10F64fromF64P6Vec128RKS_S2_:         ; @_Z10F64fromF64P6Vec128RKS_S2_
	.cfi_startproc
; %bb.0:
	; InlineAsm Start

	ld1.4s	{ v0 }, [x1]
	fcvtl	v1.2d, v0.2s	; lower-order F32    
	fcvtl2	v2.2d, v0.4s	; higher-order F32   
	st1.2d	{ v1, v2 }, [x0]	; [x0] = v1   

	; InlineAsm End
	ret
	.cfi_endproc
                                        ; -- End function
.subsections_via_symbols